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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
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hn29v25611a series 256m and type flash memory more than 16,057-sector (271,299,072-bit) ade-203-1275b (z) rev. 1.0 jan. 25, 2002 description the hitachi hn29v25611a series is a cmos flash memory with and type multi-level memory cells. it has fully automatic programming and erase capabilities with a single 3.0 v power supply. the functions are controlled by simple external commands. to fit the i/o card applications, the unit of programming and erase is as small as (2048 + 64) bytes. initial available sectors of hn29v25611a are more than 16,057 (98% of all sector address) and less than 16,384 sectors. features on-board single power supply (v cc ): v cc = 2.7 v to 3.6 v organization ? and flash memory: (2048 + 64) bytes (more than 16,057 sectors) ? data register: (2048 + 64) bytes multi-level memory cell ? 2 bit/per memory cell automatic programming ? sector program time: 1.0 ms (typ) ? system bus free ? address, data latch function ? internal automatic program verify function ? status data polling function automatic erase ? single sector erase time: 1.0 ms (typ) ? system bus free ? internal automatic erase verify function ? status data polling function
hn29v25611a series 2 erase mode ? single sector erase ((2048 + 64) byte unit) fast serial read access time: ? first access time: 50 m s (max) ? serial access time: 50 ns (max) low power dissipation: ? i cc1 = 2 ma (typ) (read) ? i cc2 = 20 ma (max) (read) ? i sb2 = 50 m a (max) (standby) ? i cc3 /i cc4 = 40 ma (max) (erase/program) ? i sb3 = 20 m a (max) (deep standby) the following architecture is required for data reliability. ? error correction: more than 3-bit error correction per each sector read ? spare sectors: 1.8% (290 sectors) (min) within usable sectors ordering information type no. available sector package HN29V25611AT-50 more than 16,057 sectors 12.0 18.40 mm 2 0.5 mm pitch 48-pin plastic tsop i (tfp-48da)
hn29v25611a series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc v cc nc* 1 nc* 1 nc* 1 v ss res rdy/ busy sc oe i/o0 i/o1 i/o2 i/o3 v cc v ss i/o4 i/o5 i/o6 i/o7 cde we ce nc* 1 v ss (top view) 48-pin tsop note: 1. this pin can be used as the v ss pin.
hn29v25611a series 4 pin description pin name function i/o0 to i/o7 input/output ce chip enable oe output enable we write enable cde command data enable v cc * 1 power supply v ss * 1 ground rdy/ busy ready/ busy res reset sc serial clock nc no connection note: 1. all v cc and v ss pins should be connected to a common power supply and a ground, respectively.
hn29v25611a series 5 block diagram 16384 (2048 + 64) 8 memory matrix x-decoder data register (2048 + 64) input data control sector address buffer y-address counter 2048 + 64 16057 - 16384 v ss res y-gating y-decoder read/program/erase control data input buffer ce oe we sc i/o0 to i/o7 rdy/ busy v cc cde multiplexer control signal buffer data output buffer
hn29v25611a series 6 memory map and address 3fffh 3ffeh 3ffdh 0002h 0001h 0000h 000h 2048 bytes 2048 bytes 2048 bytes 2048 bytes 2048 bytes 2048 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 16057 - 16384 sectors * 1 800h 83fh control bytes 2048 + 64 bytes column address sector address address sector address column address cycles sa (1): first cycle sa (2): second cycle ca (1): first cycle ca (2): second cycle i/o0 a0 a8 a0 a8 i/o1 a1 a9 a1 a9 i/o2 a2 a10 a2 a10 i/o3 a3 a11 a3 a11 i/o4 a4 a12 a4 i/o5 a5 a13 a5 i/o6 a6 * 2 a6 i/o7 a7 a7 notes: 1. some failed sectors may exist in the device. the failed sectors can be recognized by reading the sector valid data written in a part of the column address 800 to 83f (the specific address is tbd.). the sector valid data must be read and kept outside of the sector before the sector erase. when the sector is programmed, the sector valid data should be written back to the sector. 2. an means "don't care". the pin level can be set to either v il or v ih , referred to dc characteristics.
hn29v25611a series 7 pin function ce : ce is used to select the device. the status returns to the standby at the rising edge of ce in the reading operation. however, the status does not return to the standby at the rising edge of ce in the busy state in programming and erase operation. oe : memory data and status register data can be read, when oe is v il . we : commands and address are latched at the rising edge of we . sc: programming and reading data is latched at the rising edge of sc. res : res pin must be kept at the v ilr (v ss 0.2 v) level when v cc is turned on and off. in this way, data in the memory is protected against unintentional erase and programming. res must be kept at the v ihr (v cc 0.2 v) level during any operations such as programming, erase and read. cde : commands and data are latched when cde is v il and address is latched when cde is v ih . rdy/ busy : the rdy/ busy indicates the program/erase status of the flash memory. the rdy/ busy signal is initially at a high impedance state. it turns to a v ol level after the (40h) command in programming operation or the (b0h) command in erase operation. after the erase or programming operation finishes, the rdy/ busy signal turns back to the high impedance state. i/o0 to i/o7: the i/o pins are used to input data, address and command, and are used to output memory data and status register data. mode selection mode ce oe we sc res cde rdy/ busy * 3 i/o0 to i/o7 deep standby * 4 v ilr v oh high-z standby v ih v ihr v oh high-z output disable v il v ih v ih v ihr v oh high-z status register read* 1 v il v il v ih v ihr v oh status register outputs command write* 2 v il v ih v il v il v ihr v il v oh din notes: 1. default mode after the power on is the status register read mode (refer to status transition). from i/o0 to i/o7 pins output the status, when ce = v il and oe = v il (conventional read operation condition). 2. refer to the command definition. data can be read, programmed and erased after commands are written in this mode. 3. the rdy/ busy bus should be pulled up to v cc to maintain the v oh level while the rdy/ busy pin outputs a high impedance. 4. an means ?on? care? the pin level can be set to either v il or v ih referred to dc characteristics.
hn29v25611a series 8 command definition * 1, 2 first bus cycle second bus cycle command bus cycles operation mode* 3 data in operation mode data in data out read serial read (1) (without ca) 3 write 00h write sa (1)* 4 (with ca) 3 + 2h* 6 write 00h write sa (1)* 4 serial read (2) 3 write f0h write sa (1)* 4 read identifier codes 1 write 90h read id* 8, 9 data recovery read 1 write 01h read recovery data auto erase single sector 4 write 20h write sa (1)* 4 auto program program (1) (without ca* 7 ) 4 write 10h write sa (1)* 4 (with ca* 7 ) 4 + 2h* 6 write 10h write sa (1)* 4 program (2)* 10 4 write 1fh write sa (1)* 4 program (3) (control bytes)* 7 4 write 0fh write sa (1)* 4 program (4) (withoutca* 7 ) 4 write 11h write sa (1)* 4 (with ca* 7 ) 4 + 2h* 6 write 11h write sa (1)* 4 reset 1 write ffh clear status register 1 write 50h data recovery write 4 write 12h write sa (1)* 4
hn29v25611a series 9 third bus cycle fourth bus cycle command bus cycles operation mode data in operation mode data in read serial read (1) (without ca) 3 write sa (2)* 4 (with ca) 3 + 2h* 6 write sa (2)* 4 write ca (1)* 5 serial read (2) 3 write sa (2)* 4 read identifier codes 1 data recovery read 1 auto erase single sector 4 write sa (2)* 4 write b0h* 11 auto program program (1) (without ca* 7 ) 4 write sa (2)* 4 write 40h *11, 12 (with ca* 7 ) 4 + 2h* 6 write sa (2)* 4 write ca (1) program (2)* 10 4 write sa (2)* 4 write 40h *11, 12 program (3) (control bytes)* 7 4 write sa (2)* 4 write 40h *11, 12 program (4) (withoutca* 7 ) 4 write sa (2)* 4 write 40h *11, 12 (with ca* 7 ) 4 + 2h* 6 write sa (2)* 4 write ca (1) reset 1 clear status register 1 data recovery write 4 write sa (2)* 4 write 40h *11, 12
hn29v25611a series 10 fifth bus cycle sixth bus cycle command bus cycles operation mode data in operation mode data in read serial read (1) (without ca) 3 (with ca) 3 + 2h* 6 write ca (2)* 5 serial read (2) 3 read identifier codes 1 data recovery read 1 auto erase single sector 4 auto program program (1) (without ca* 7 ) 4 (with ca* 7 ) 4 + 2h* 6 write ca (2)* 5 write 40h *11, 12 program (2)* 10 4 program (3) (control bytes)* 7 4 program (4) (withoutca* 7 )4 (with ca* 7 ) 4 + 2h* 6 write ca (2) write 40h *11, 12 reset 1 clear status register 1 data recovery write 4 notes: 1. commands and sector address are latched at rising edge of we pulses. program data is latched at rising edge of sc pulses. 2. the chip is in the read status register mode when res is set to v ihr first time after the power up. 3. refer to the command read and write mode in mode selection. 4. sa (1) = sector address (a0 to a7), sa (2) = sector address (a8 to a13). 5. ca (1) = column address (a0 to a7), ca (2) = column address (a8 to a11). (0 a11 to a0 83fh) 6. the variable h is the input number of times of set of ca (1) and ca (2) (1 h 2048 + 64). set of ca (1) and ca (2) can be input without limitation. 7. by using program (1) and (3), data can additionally be programmed maximum 15 times for each sector before erase. 8. id = identifier code; manufacturer code (07h), device code (9ah). 9. the manufacturer identifier code is output when cde is low and the device identifier code is output when cde is high. 10. before program (2) operations, data in the programmed sector must be erased. 11. no commands can be written during auto program and erase (when the rdy/ busy pin outputs a v ol ). 12. the fourth or sixth cycle of the auto program comes after the program data input is complete.
hn29v25611a series 11 mode description read serial read (1): memory data d0 to d2111 in the sector of address sa is sequentially read. output data is not valid after the number of the sc pulse exceeds 2112. when ca is input, memory data d (m) to d (m + j) in the sector of address sa is sequentially read. then output data is not valid after the number of the sc pulse exceeds (2112 to m). the mode turns back to the standby mode at any time when ce is v ih . serial read (2): memory data d2048 to d2111 in the sector of address sa is sequentially read. output data is not valid after the number of the sc pulse exceeds 64. the mode turns back to the standby mode at any time when ce is v ih . automatic erase single sector erase: memory data d0 to d2111 in the sector of address sa is erased automatically by internal control circuits. after the sector erase starts, the erasure completion can be checked through the rdy/ busy signal and status data polling. all the bits in the sector are "1" after the erase. the sector valid data stored in a part of memory data d2048 to d2111 must be read and kept outside of the sector before the sector erase. automatic program program (1): program data pd0 to pd2111 is programmed into the sector of address sa automatically by internal control circuits. when ca is input, program data pd (m) to pd (m + j) is programmed from ca into the sector of address sa automatically by internal control circuits. by using program (1), data can additionally be programed 15 times for each sector before the following erase. when the column is programmed, the data of the column must be [ff]. after the programming starts, the program completion can be checked through the rdy/ busy signal and status data polling. programmed bits in the sector turn from "1" to "0" when they are programmed. the sector valid data should be included in the program data pd2048 to pd2111. program (2): program data pd0 to pd2111 is programmed into the sector of address sa automatically by internal control circuits. after the programming starts, the program completion can be checked through the rdy/ busy signal and status data polling. programmed bits in the sector turn from "1" to "0" when they are programmed. the sector must be erased before programming. the sector valid data should be included in the program data pd2048 to pd2111. program (3): program data pd2048 to pd2111 is programmed into the sector of address sa automatically by internal control circuits. by using program (3), data can additionally be programed 15 times for each sector befor the following erase. when the column is programmed, the data of the column must be [ff]. after the programming starts, the program completion can be checked through the rdy/ busy signal and status data polling. programmed bits in the sector turn from "1" to "0" when they are programmed.
hn29v25611a series 12 program (4): program data pd0 to pd2111 is programmed into the sector of address sa automatically by internal control circuits. when ca is input, program data pd (m) to pd (m + j) is programmed from ca into the sector of address sa automatically by internal control circuits. by using program (4), data can be rewritten for each sector before the following erase. so the column data before programming operation are either "1" or "0". in this mode, e/w number of times must be counted whenever program (4) execute. after the programming starts, the program completion can be checked through the rdy/ busy signal and status data polling. the sector valid data should be included in the program data pd2048 to pd2111. memory array 16383 sector address 0 0 2111 register serial read (1) (without ca) program (1) (without ca) program (2) 16383 sector address 0 0 2111 register serial read (2) program (3) 2048 memory array 16383 sector address 0 0 2111 register serial read (1) (with ca) program (1) (with ca) column address memory array status register read the status returns to the status register read mode from standby mode, when ce and oe is v il . in the status register read mode, i/o pins output the same operation status as in the status data polling defined in the function description. identifier read the manufacturer and device identifier code can be read in the identifier read mode. the manufacturer and device identifier code is selected with cde v il and v ih , respectively.
hn29v25611a series 13 data recovery read when the programming was an error, the program data can be read by using data recovery read. when an additional programming was an error, the data compounded of the program data and the origin data in the sector address sa can be read. output data are not valid after the number of sa pulse exeeds 2112. the mode turns back to the standby mode at any time when ce is v ih . the read data are invalid when addresses are latched at a rising edge of we pulse after the data recovery read command is written. data recovery write when the programming into a sector of address sa was an error, the program data can be rewritten automatically by internal control circuit into the other selected sector of address sa? since the data recovery write mode is internally program (4) mode, rewritten sector of address sa?needs no sector erase before rewrite. after the data recovery write mode starts, the program completion can be checked through the rdy/ busy signal and the status data polling.
hn29v25611a series 14 command/address/data input sequence serial read (1) (with ca before sc) 00h sa (1) sa (2) ca (1) ca (2) ca (1)' ca (2)' low data output data output command /address cde we sc serial read (1) (with ca after sc) 00h sa (1) sa (2) ca (1)' ca (2)' ca (1) ca (2) low data output data output data output command /address cde we sc serial read (1) (without ca), (2) 00h/f0h sa (1) sa (2) low data output command/address cde we sc single sector erase 20h b0h sa (1) sa (2) command/address cde we sc low erase start
hn29v25611a series 15 program (1), (4) (with ca before sc) 10h/11h sa (1) sa (2) ca (1) ca (2) ca (1)' ca (2)' 40h low data input data input program start command /address cde we sc program (1), (4) (with ca after sc) 10h/11h sa (1) sa (2) ca (1) ca (2) 40h low data input data input program start ca (1)' ca (2)' data input command /address cde we sc program (1), (4) (without ca) data input 10h/11h 40h sa (1) sa (2) command/address cde we sc low program start program (2) data input 1fh 40h sa (1) sa (2) command/address cde we sc low program start
hn29v25611a series 16 program (3) data input 0fh 40h sa (1) sa (2) command/address cde we sc low program start id read mode 90h command/address cde we sc low manufacture code output manufacture code output device code output data recovery read mode 01h command/address cde we sc low data output data recovery write mode 12h 40h sa (1) sa (2) command/address cde we sc low program start
hn29v25611a series 17 status transition deep standby power off v cc ce ce status register read status register read oe oe status register read oe 00h/f0h ffh sa (1), sa (2) oe , sc sc, cde sc, cde sc, cde oe sc ca(1) ca(2) ca(1)' ca(2)' ca(1)' ca(2)' ca(1) ca(2) res id read 90h cde , oe output disable standby error standby ce ffh ce sector erase setup sector address input 20h sa (1), sa (2) erase start b0h ffh erase finish status register read oe program (1)/(4) setup sector address input column address input 10h /11h sa (1), sa (2) program start program data input pd0 to pd2111 pd(m) to pd(m+j) ffh program finish data recovery read setup 01h* 1 data recovery write setup sector address input 12h* 1 ffh 40h sa(1) sa(2) data recovery read oe , sc read (1) / (2) setup sector address input read (1) / (2) column address input id read setup status register read oe program (2)/(3) setup sector address input 1fh /0fh sa (1), sa (2) program start program data input pd0 to pd2111*3 ffh ffh* 2 ce * 2 program finish busy 40h 40h output disable status register clear 50h error program error or erase error notes: 1. (01h)/(12h) data recovery read/write can be used only for program (1), (2), (3), (4) errors. 2. when reset is done by ce or ffh, error status flag is cleared. 3. when program (3) mode, input data is pd2048 to pd2111.
hn29v25611a series 18 absolute maximum ratings parameter symbol value unit notes v cc voltage v cc ?.6 to +4.6 v 1 v ss voltage v ss 0v all input and output voltages vin, vout ?.6 to +4.6 v 1, 2 operating temperature range topr 0 to +70 ?c storage temperature range tstg ?5 to +125 ?c 3 storage temperature under bias tbias ?0 to +80 ?c notes: 1. relative to v ss . 2. vin, vout = ?.0 v for pulse width 20 ns. 3. device storage temperature range before programming. capacitance (ta = 25?c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance cin 6 pf vin = 0 v output capacitance cout 12 pf vout = 0 v
hn29v25611a series 19 dc characteristics (v cc = 2.7 v to 3.6 v, ta = 0 to +70?c) parameter symbol min typ max unit test conditions input leakage current i li 2 m a vin = v ss to v cc output leakage current i lo 2 m a vout = v ss to v cc standby v cc current i sb1 0.3 1 ma ce = v ih i sb2 ?050 m a ce = v cc 0.2 v, res = v cc 0.2 v deep standby v cc current i sb3 ?20 m a res = v ss 0.2 v operating v cc current i cc1 2 20 ma iout = 0 ma, f = 0.2 mhz i cc2 10 20 ma iout = 0 ma, f = 20 mhz operating v cc current (program) i cc3 20 40 ma in programming operating v cc current (erase) i cc4 20 40 ma in erase input voltage v il ?.3* 1, 2 0.8 v v ih 2.0 v cc + 0.3* 3 v input voltage ( res pin) v ilr ?.2 0.2 v v ihr v cc ?0.2 v cc + 0.2 v output voltage v ol 0.4 v i ol = 2 ma v oh 2.4 vi oh = ? ma notes: 1. v il min = ?.0 v for pulse width 50 ns in the read operation. v il min = ?.0 v for pulse width 20 ns in the read operation. 2. v il min = ?.6 v for pulse width 20 ns in the erase/data programming operation. 3. v ih max = v cc + 1.5 v for pulse width 20 ns. if v ih is over the specified maximum value, the operations are not guaranteed. ac characteristics (v cc = 2.7 v to 3.6 v, ta = 0 to +70?c) test conditions input pulse levels: 0.4 v/2.4 v input pulse levels for res : 0.2 v/v cc ?0.2 v input rise and fall time: 5 ns output load: 1 ttl gate + 100 pf (including scope and jig.) reference levels for measuring timing: 0.8 v, 1.8 v
hn29v25611a series 20 power on and off, serial read mode parameter symbol min typ max unit test conditions notes write cycle time t cwc 120 ns serial clock cycle time t scc 50ns ce setup time t ces 0 ns ce hold time t ceh 0 ns write pulse time t wp 60ns ce = v il , oe = v ih write pulse high time t wph 40ns address setup time t as 50ns address hold time t ah 10ns data setup time t ds 50ns data hold time t dh 10ns sc to output delay t sac 50ns ce = oe = v il , we = v ih oe setup time for sc t oes 0 ns oe low to output low-z t oel 0 40 ns oe setup time before read t oer 100 ns oe setup time before command write t oews 0 ns sc to output hold t sh 15ns ce = oe = v il , we = v ih oe high to output float t df 40ns ce = v il , we = v ih 1 we to sc delay time t wsd 50 m s2 res to ce setup time t rp 0.3 ms sc to oe hold time t soh 50ns sc pulse width t sp 20ns sc pulse low time t spl 20ns sc setup time for ce t scs 0 ns cde setup time for we t cds 0 ns cde hold time for we t cdh 20ns v cc setup time for res t vrs 1 m s ce = v ih res to v cc hold time t vrh 1 m s ce = v ih ce setup time for res t cesr 1 m s rdy/ busy undefined for v cc off t dfp 0 ns res high to device ready t bsy 0.3 ms ce pulse high time t cph 200 ns ce , we setup time for res t cwrs 0 ns res to ce , we hold time t cwrh 0 ns
hn29v25611a series 21 parameter symbol min typ max unit test conditions notes sc setup for we t sw 50ns ce hold time for oe t coh 0 ns sa (2) to ca (2) delay time t scd 30 m s rdy/ busy setup for sc t rs 200 ns time to device busy t db 150 ns busy time on read mode t rbsy ?5 m s notes: 1. t df is a time after which the i/o pins become open. 2. t wsd (min) is specified as a reference point only for sc, if t wsd is greater than the specified t wsd (min) limit, then access time is controlled exclusively by t sac .
hn29v25611a series 22 program, erase and erase verify parameter symbol min typ max unit test conditions note write cycle time t cwc 120 ns serial clock cycle time t scc 50ns ce setup time t ces 0 ns ce hold time t ceh 0 ns write pulse time t wp 60ns write pulse high time t wph 40ns address setup time t as 50ns address hold time t ah 10ns data setup time t ds 50ns data hold time t dh 10ns oe setup time before command write t oews 0 ns oe setup time before status polling t oeps 40ns oe setup time before read t oer 100 ns time to device busy t db 150 ns auto erase time t ase 1.0 10.0 ms auto program time program(1), (3) t asp 1.5 20.0 ms program(2) t asp 1.0 20.0 ms program(4), data recovery write t asp 2.0 30.0 ms we to sc delay time t wsd 50 m s ce pulse high time t cph 200 ns sc pulse width t sp 20ns sc pulse low time t spl 20ns data setup time for sc t sds 0 ns data hold time for sc t sdh 30ns cde = v il sc setup for we t sw 50ns sc setup for ce t scs 0 ns sc hold time for we t schw 20ns
hn29v25611a series 23 parameter symbol min typ max unit test conditions note ce to output delay t ce 120 ns oe to output delay t oe 60ns oe high to output float t df 40ns 1 res to ce setup time t rp 0.3 ms cde setup time for we t cds 0 ns cde hold time for we t cdh 20ns cde setup time for sc t cdss 1.5 m s cde hold time for sc t cdsh 30ns next cycle ready time t rdy 0 ns cde to oe hold time t cdoh 50ns cde to output delay t cdac 50ns cde to output invalid t cdf 100 ns ce hold time for oe t coh 0 ns oe setup time for sc t oes 0 ns oe low to output low-z t oel 0 40 ns sc to output delay t sac 50ns sc to output hold t sh 15ns rdy/ busy setup for sc t rs 200 ns busy time on read mode t rbsy ?5 m s note: 1. t df is a time after which the i/o pins become open.
hn29v25611a series 24 timing waveforms power on and off sequence t vrs t rp t ces t bsy t ceh t cesr t rp t bsy t ces t ceh t vrh t dfp t cwrh t cesr t cwrs v cc ce we res rdy / busy * 1 * 2 * 1 high-z ready notes: 1. res must be kept at the v ilr level referred to dc characteristics at the rising and falling edges of v cc to guarantee data stored in the chip. 2. res must be kept at the v ihr level referred to dc characteristics while i/o7 outputs the v ol level in the status data polling and rdy/ busy outputs the v ol level. 3. : undefined
hn29v25611a series 25 serial read (1) (2) timing waveform ce oe we cde res t ces t cwc t cwc t ceh t cph t wph t oer t wph t wp t wp t wp t sac t sac t sac t sp t oes sc t wsd t scc t scc t soh i/o0 to i/o7 t scs t ds t rp t db t rbsy t rs t as t as t dh t ds t cds t df t sac t cdh t wp t coh t dh t ah t ah t oel high-z rdy / busy d0out/d2048out d1out/d2049out d2111out/d2111out 00h /f0h sa(1) notes: 1. the status returns to the standby at the rising edge of ce . 2. output data is not valid after the number of the sc pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectiv ely. 3. after any commands are written, the status can return to the standby after the command ffh is input and ce turns to the v ih level. t oews t cds t cds t cdh * 2 * 2 * 1 * 3 t spl t sh t sh ffh sa(2) serial read (1) with ca before sc timing waveform ce oe we cde res t ces t cwc t cwc t cwc t cwc t cds t cph t ceh t wp t cdh t wph t wph t oer t wph t wph t wp t wp t wp t wp t wp sc t scd t wsd t scc t scc t scc t scc t oes t oes t wph t cwc t oews i/o0 to i/o7 t scs t ds t as t as t as t as t ah t ah t as t sh t as t ah t ah t oel t ah t ah t sh t sh t sac t sac t sac t sac t df t sp t rp t rbsy t db t rs t dh t oer t wp t sw t sp t spl t wp t coh h-1 cycle high-z rdy / busy d(n)out d(n+1)out d(n+i)out 00h sa(1) ca(1) ca(2) ca(2)' ca(1)' d(m)out d(m+1)out d(m+j)out ffh notes: 1. the status returns to the standby at the rising edge of ce . 2. output data is not valid after the number of the sc pulse exceeds (2112-n). (i 2111-n, 0 n 2111) 3. output data is not valid after the number of the sc pulse exceeds (2112-m). (j 2111-m, 0 m 2111) 4. after any commands are written, the status can return to the standby after the command ffh is input and ce turns to the v ih level. 5. this interval can be repeated (h-1) cycle. (1 h 2048 + 64) t oews t cds t cds t cdh * 2 * 2 * 3 * 3 * 1 * 5 * 4 t soh t soh t spl t oel t sac t sac t sac t df t ds t dh t sac t sh sa(2)
hn29v25611a series 26 serial read (1) with ca after sc timing waveform ce oe we cde res t ces t cwc t cwc t cds t cph t ceh t wp t cdh t wph t wph t oer t wp t wp t wp sc t scc t scc t wsd t oes t scc t scc t oes t oel t wph t cwc t oews i/o0 to i/o7 t scs t ds t as t as t sac t sp t sh t ah t ah t sh t sh t spl t sac t sac t sac t df t ah t ah t as t as t rp t db t rbsy t rs t dh t oer t wp t sw t sp t spl t wp t coh h cycle high-z rdy / busy d0out d1out d(k)out 00h sa(1) ca(2) ca(1) d(m)out d(m+1)out d(m+j)out ffh notes: 1. the status returns to the standby at the rising edge of ce . 2. output data is not valid after the number of the sc pulse exceeds 2112. (0 k 2111) 3. output data is not valid after the number of the sc pulse exceeds (2112-m). (j 2111-m, 0 m 2111) 4. after any commands are written, the status can return to the standby after the command ffh is input and ce turns to the v ih level. 5. this interval can be repeated h cycle. (1 h 2048 + 64) t oews t cds t cds t cdh * 2 * 3 * 3 * 1 * 5 * 2 * 4 t soh t soh t oel t sac t sac t sac t df t ds t dh t sac t sh sa(2) erase and status data polling timing waveform (sector erase) ce oe we cde res t ces t cwc t cwc t cwc t ceh t oeps t ce t oe t rdy t ase t wph t wph t wph t wp t wp t wp t wp t cdh sc t schw i/o0 to i/o7 t scs t ds t ds t db t rp t as t as t dh t dh t df t df t cds t ah t ah high-z high-z rdy / busy io7 = v oh io7 = v ol 20h sa(1) sa(2) notes: 1. any commands,including reset command ffh, cannot be input while rdy/ busy outputs a v ol . 2. the status returns to the standby status after rdy/ busy returns to high-z. t oews t cds t cds t cds t cdh t cdh b0h * 2 * 1
hn29v25611a series 27 program (1) and status data polling timing waveform * 1 ce we res rdy / busy oe cde sc i/o0 to i/o7 t ces t oews t cwc t wph t wp t cds t cds t scs t rp t cdh t ds t cdh t oe t cdss t wp t wp t sw t schw t cdh t wp t spl t scc t wph t ceh t ce t rdy t cwc t db t oeps t asp t dh t as t as t ah t sp t sp t ds t dh 40h 10h pd0 pd1 pd2111 i/o7 = v ol i/o7 = v oh sa (1) sa (2) high-z high-z * 2 * 3 t df t df t cds notes: 1. the programming operation is not guranteed when the number of the sc pulse exceeds 2112. 2. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 3. the status returns to the standby status after rdy/ busy returns to high-z. 4. by using program (1), data can be programmed additionally for each sector before erase. t ah t sdh t sds
hn29v25611a series 28 program (1) with ca before sc and status data polling timing waveform ce sc i/o0 to i/o7 res rdy / busy oe we cde notes: 1. the programming operation is not guaranteed when the number of the sc pulse exceeds (2112 e n).(i 2111 e n, 0 n 2111) 2. the programming operation is not guaranteed when the number of the sc pulse exceeds (2112 e m).(j 2111 e m, 0 m 2111) 3. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 4. the status returns to the standby status after rdy/ busy returns to high-z. 5. by using program (1), data can be programmed additionally for each sector before erase. 6. this interval can be repeated (h e 1) cycle.(1 h 2048 + 64) t ces t wp t cds t cds t cdh t cdh t cdss t cdh t cdsh t as t as t sds t ds t db t scc t ah t ah t sdh t dh t df t df t cds t sw t cdss t ds t as t as t as t as t sds t dh t ah t ah t ah t ah t scs t wp t rp t wp t wp t wp t wp t wp t wp t ceh t ce t cdh t schw t oeps t rdy t oe t sw t cds t wph t cwc t oews t cwc t cwc t cwc t cwc t wph t wph t wph t wph high-z high-z* 4 10h sa(1) sa(2) ca(1) ca(2) ca(1)' ca(2)' pd(n) pd(n+1) pd(n+i)* 1 * 1 * 2 * 3 pd(m) pd(m+1) pd(m+j)* 2 he1 cycle* 6 i/o7=v ol i/o7=v oh t sdh t spl t sp t sp t sp t sp t spl t scc 40h t asp program (1) with ca after sc and status data polling timing waveform ce sc i/o0 to i/o7 res rdy / busy oe we cde notes: 1. the programming operation is not guaranteed when the number of the sc pulse exceeds 2112.(0 k 2111) 2. the programming operation is not guaranteed when the number of the sc pulse exceeds (2112 e m).(j 2111 e m, 0 m 2111) 3. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 4. the status returns to the standby status after rdy/ busy returns to high-z. 5. by using program (1), data can be programmed additionally for each sector before erase. 6. this interval can be repeated h cycle.(1 h 2048 + 64) t ces t wp t cds t cds t cdh t cdh t cdss t cdh t cdsh t as t as t sds t ds t db t scc t ah t ah t sdh t dh t df t df t cds t sw t cdss t ds t as t as t sds t dh t ah t ah t sdh t scs t wp t rp t wp t wp t wp t wp t ceh t ce t cdh t schw t oeps t rdy t oe t sw t cds t wph t cwc t oews t cwc t cwc t wph t wph high-z high-z* 4 10h sa(1) sa(2) pd0 pd1 ca(1) ca(2) pd(k)* 1 * 1 * 2 * 3 pd(m) pd(m+1) pd(m+j)* 2 h cycle* 6 i/o7=v ol i/o7=v oh t spl t sp t sp t sp t sp t spl t scc 40h t asp
hn29v25611a series 29 program (2) and status data polling timing waveform * 1 ce we res rdy / busy oe cde sc i/o0 to i/o7 t ces t oews t cwc t wph t wp t cds t cds t scs t rp t cdh t ds t cdh t oe t cdss t wp t wp t sw t schw t cdh t wp t spl t scc t wph t ceh t cds t ce t rdy t cwc t db t oeps t asp t dh t as t as t ah t sp t sp t ds t dh 40h 1fh pd0 pd1 pd2111 i/o7 = v ol i/o7 = v oh sa (1) sa (2) high-z high-z * 2 * 3 t df t df notes: 1. the programming operation is not guranteed when the number of the sc pulse exceeds 2112. 2. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 3. the status returns to the standby status after rdy/ busy returns to high-z. 4. by using program (2), the programmed data of each sector must be erased before programming next data. t ah t sdh t sds
hn29v25611a series 30 program (3) and status data polling timing waveform * 1 ce we res rdy / busy oe cde sc i/o0 to i/o7 t ces t oews t cwc t wph t wp t cds t cds t scs t rp t cdh t ds t cdh t oe t cdss t wp t wp t sw t schw t cdh t wp t spl t scc t ceh t cds t ce t rdy t cwc t db t oeps t asp t dh t as t as t ah t sp t sp t ds t dh 40h 0fh pd2048 pd2049 pd2111 i/o7 = v ol i/o7 = v oh sa (1) sa (2) high-z high-z * 2 * 3 t df t df notes: 1. the programming operation is not guranteed when the number of the sc pulse exceeds 64. 2. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 3. the status returns to the standby status after rdy/ busy returns to high-z. 4. by using program (3), the data can be programmed additionally for each sector before erase. t ah t sdh t sds
hn29v25611a series 31 program (4) and status data polling timing waveform * 1 ce we res rdy / busy oe cde sc i/o0 to i/o7 t ces t oews t cwc t wph t wp t cds t cds t scs t rp t db t db t rs t rbsy t cdh t ds t cdh t wsd t oe t cdss t wp t wp t sw t schw t cdh t cds t wp t spl t scc t wph t ceh t ce t rdy t cwc t db t oeps t asp t dh t as t as t ah t sp t sp t ds t dh 40h 11h pd0 pd1 pd2111 i/o7 = v ol i/o7 = v oh sa (1) sa (2) high-z high-z * 2 * 3 t df t df notes: 1. the programming operation is not guranteed when the number of the sc pulse exceeds 2112. 2. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 3. the status returns to the standby status after rdy/ busy returns to high-z. 4. by using program (4), data can be rewritten for each sector. t ah t sdh t sds
hn29v25611a series 32 program (4) with ca before sc and status data polling timing waveform ce sc i/o0 to i/o7 res rdy / busy oe we cde notes: 1. the programming operation is not guaranteed when the number of the sc pulse exceeds (2112 e n).(i 2111 e n, 0 n 2111) 2. the programming operation is not guaranteed when the number of the sc pulse exceeds (2112 e m).(j 2111 e m, 0 m 2111) 3. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 4. the status returns to the standby status after rdy/ busy returns to high-z. 5. by using program (4), data can be rewritten for each sector. 6. this interval can be repeated (h e 1) cycle.(1 h 2048 + 64) t ces t wp t cds t cds t cdh t cdh t wsd t cdss t cdh t cdsh t as t as t sds t ds t db t scc t ah t ah t sdh t dh t df t df t cds t sw t cdss t ds t as t as t as t as t sds t dh t ah t ah t ah t ah t scs t wp t rp t db t rbsy t rs t wp t wp t wp t wp t wp t wp t ceh t ce t cdh t schw t oeps t rdy t oe t sw t cds t wph t cwc t oews t cwc t cwc t cwc t cwc t wph t wph t wph t wph high-z high-z* 4 11h sa(1) ca(1) ca(2) ca(1)' ca(2)' pd(n+1) pd(n+i)* 1 * 1 * 2 * 3 pd(m) pd(m+1) pd(m+j)* 2 he1 cycle* 6 i/o7=v ol i/o7=v oh t sdh t spl t sp t sp t sp t sp t spl t scc 40h sa(2) pd(n) t asp program (4) with ca after sc and status data polling timing waveform ce sc i/o0 to i/o7 res rdy / busy oe we cde notes: 1. the programming operation is not guaranteed when the number of the sc pulse exceeds 2112.(0 k 2111) 2. the programming operation is not guaranteed when the number of the sc pulse exceeds (2112 e m).(j 2111 e m, 0 m 2111) 3. any commands, including reset command ffh, cannot be input while rdy/ busy is v ol . 4. the status returns to the standby status after rdy/ busy returns to high-z. 5. by using program (4), data can be rewritten for each sector. 6. this interval can be repeated h cycle.(1 h 2048 + 64) t ces t wp t cds t cds t cdh t cdh t wsd t cdss t cdh t cdsh t as t as t sds t ds t db t scc t ah t ah t sdh t dh t df t df t cds t sw t cdss t ds t as t as t sds t dh t ah t ah t sdh t scs t wp t rp t db t rs t rbsy t wp t wp t wp t wp t ceh t ce t cdh t schw t oeps t rdy t oe t sw t cds t wph t cwc t oews t cwc t cwc t wph t wph high-z high-z* 4 11h sa(1) pd1 ca(1) ca(2) pd(k)* 1 * 1 * 2 * 3 pd(m) pd(m+1) pd(m+j)* 2 h cycle* 6 i/o7=v ol i/o7=v oh t spl t sp t sp t sp t sp t spl t scc 40h sa(2) pd0 t asp
hn29v25611a series 33 id and status register read timing waveform ce oe we cde res t ces t ce t coh t coh t wp t schw sc i/o0 to i/o7 t scs t dh t df t oe t scs t oe t cdac t cdac t cdf t cdf t rp t df high-z rdy / busy status register 90h manufacturer code manufacturer code device code note: 1. the status returns to the standby at the rising edge of ce . t oews t oeps t cdh t cdoh t cds * 1 * 1 t ds
hn29v25611a series 34 data recovery read timing waveform ce oe we cde res t ces t cph t coh t ceh t wp t wp t cdh t scc t sp t sac t sac t scc t soh sc i/o0 to i/o7 t scs t oel t oes t cds t ds t dh high-z high rdy / busy 01h ffh d0out d1out d2111out notes: 1. the status returns to the standby at the rising edge of ce . 2. output data is not valid after the number of the sc pulse exceed 2112 in the recovery data read mode. 3. after any commands are written, the status can turns to the standby after the command ffh is input and ce turns to the v ih level. t oews t oer t sh t sh t sac t sac t cds * 3 * 1 * 2 * 2 t ds t cdh t dh t spl t df
hn29v25611a series 35 data recovery write timing waveform ce oe we cde res t ces t cwc t cwc t cwc t ceh t oeps t asp t ce t oe t rdy t wph t wph t wph t wp t wp t wp t wp t cdh sc t schw i/o0 to i/o7 t scs t ds t ds t db t as t as t dh t dh t df t df t cds t ah t ah high-z high high-z rdy / busy io7 = v oh io7 = v ol 12h sa(1) sa(2) notes: 1. any commands,including reset command ffh, cannot be input while rdy/ busy is v ol . 2. the status returns to the standby status after rdy/ busy returns to high-z. t oews t cds t cds t cds t cdh t cdh * 2 * 1 40h
hn29v25611a series 36 clear status register timing waveform we cde res rdy / busy sc i/o0 to i/o7 oe ce t ces t cds t scs t ds t dh t wp t cdh t wph t ceh t cds t cdh t wp t cph t ces t cdh t wp t scs t ds t dh tds tdh high-z note 1. the status returns to the standby at the rising edge of ce . * 1 next command next command 50h t oews high t oews t cds
hn29v25611a series 37 function description status register: the hn29v25611a outputs the operation status data as follows: i/o7 pin outputs a v ol to indicate that the memory is in either erase or program operation. the level of i/o7 pin turns to a v oh when the operation finishes. i/o5 and i/o4 pins output v ol s to indicate that the erase and program operations complete in a finite time, respectively. if these pins output v oh s, it indicates that these operations have timed out. if i/o6 pin outputs v oh , it indicates a possibility that can be corrected by ecc, choose data correction by ecc or not by reading out the data. when these pins monitor, i/o7 pin must turn to a v oh . to execute other erase and program operation, the status data must be cleared after a time out occurs. from i/o0 to i/o3 pins are reserved for future use. the pins output v ol s and should be masked out during the status data read mode. the function of the status register is summarized in the following table. i/o flag definition definition i/o7 ready/ busy v oh = ready, v ol = busy i/o6 program/erase ecc check when i/o7 outputs v oh , v oh = ecc available, v ol = ecc not available. i/o5 erase check v oh = fail, v ol = pass i/o4 program check v oh = fail, v ol = pass i/o3 reserved outputs a v ol and should be masked out during the status data poling mode. i/o2 reserved i/o1 reserved i/o0 reserved ecc applicability i/o7 i/o6 i/o5 i/o4 system data correction by ecc v oh v oh v oh v ol needed v oh v ol v oh v ol not needed. sector replacement v oh v oh v ol v oh needed v oh v ol v ol v oh not needed. sector replacement this device needs to be corrected failure data by ecc on system or spare sectors, by reading out again the failure sector data when program/erase error occures.
hn29v25611a series 38 requirement for system specifications program/erase endurance: 10 5 cycles item min typ max unit usable sectors (initially) 16,057 16,834 sector spare sectors 290 sector ecc (error correction code) 3 bit/sector
hn29v25611a series 39 unusable sector initially, the hn29v25611a includes unusable sectors. the unusable sectors must be distinguished from the usable sectors by the system as follows. 1. check the partial invalid sectors in the devices on the system. the usable sectors were programmed the following data. refer to the flowchart ?ndication of unusable sectors? initial data of usable sectors column address 0h to 81fh 820h 821h 822h 823h 824h 825h 826h to 83fh data ffh 1ch 71h c7h 1ch 71h c7h ffh 2. do not erase and program to the partial invalid sectors by the system. sector number = 0 read data bad sector* 2 sector number = sector number + 1 column address = 820h to 825h ye s ye s no no check data* 1 sector number = 16,383 start end notes: 1. refer to table "initial data of usable sectors". 2. bad sectors are installed in system. the unusable sector indication flow
hn29v25611a series 40 requirements for high system reliability the device may fail during a program, erase or read operation due to write or erase cycles. the following architecture will enable high system reliability if a failure occurs. 1. for an error in read operation: an ecc (error correction code) or a similar function which can correct 3-bits per each sectors is required for data reliability. when error occurs, data must not be corrected by replacing to spare sector. 2. for errors in program or erase operations: the device may fail during a program or erase operation due to write or erase cycles. the status register indicates if the erase and program operation complete in a finite time. when an error occured in the sector, try to reprogram the data into another sector. avoid further system access to the sector that error happens. typically, recommended number of a spare sectors are 1.8% (290 sectors (min)) of initial usable 16,057 sectors (min) by each device. for the reprogramming, do not use the data from the failed sectors, because the data from the failed sectors are not fixed. so the reprogram data must be the data reloaded from the external buffer, or use the data recovery read mode or the data recovery write mode (see the ?ode description?and under figure ?pare sector replacement flow after program error?. to avoid consecutive sector failures, choose addresses of spare sectors as far as possible from the failed sectors. in this case, 10 5 cycles of program/erase endurance is guaranteed.
hn29v25611a series 41 program start program end clear status register program start program end load data from external buffer data recovery read data recovery write check rdy/ busy set an usable sector check rdy/ busy set another usable sector ye s no check status check status: status register read ye s no check status start end spare sector replacement flow after program error
hn29v25611a series 42 for errors in program or erase operations the device may fail during a program or erase operation. failure mode can be confirmed by read out the status register after complete the erase and program operations. there are two failure modes specified by each codes: 1: status register error flag: i/o6 = v ol replace sector under the ?pare sectors replacement flow at status register i/o6 read? replacement must be applied to one sector(2k bytes) which contains failure bits. 2: status register error flag: i/o6 = v oh escape the program data temporary under the ?eplacement flow at status register i/o6 read? if failure data can be corrected by ecc, do not replace to spare sector. if failure data can not be corrected by ecc, replace to spare sector. replacement must be applied to one sector(2k bytes) which contains failure bits. program start program end sector replacement sector replacement program end program end check rdy/ busy set an usable sector ye s ye s ye s no no check status ye s no check status check status check ecc check i/o6 start end escape program deta* 1 read error sector v ol v oh note: 1. refer to 'spare sector replacement flow after program error' to escape the deta. check status: status register read check i/o6: i/o6 output monitor check ecc: correct by ecc? no spare sectors replacement flow at status register i/o6 read
hn29v25611a series 43 memory structure 16,384 sectors sector 2,112 bytes (16,896 bits) byte (8 bits) bit bit: minimum unit of data. byte: input/output data unit in programming and reading. (1 byte = 8 bits) sector: page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits) device: 1 device = 16,384 sectors.
hn29v25611a series 44 package dimensions hn29v25611at series (tfp-48da) 0.08 0.08 m 0.50 12.00 *0.22 0.08 20.00 0.20 0.05 0.05 1.20 max 18.40 0 e 8 48 124 25 12.40 max 0.45 max *0.17 0.05 0.50 0.10 0.80 0.20 0.06 0.125 0.04 hitachi code jedec eiaj mass (reference value) tfp-48da conforms conforms 0.52 g unit: mm *dimension including the plating thickness base material dimension
hn29v25611a series 45 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 2001. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-538-6533/538-8577 fax : <65>-538-6933/538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-(2)-735-9218 fax : <852>-(2)-730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen postfach 201,d-85619 feldkirchen germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colophon 5.0

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